Xilinx? 7 series FPGAs CLBs專題介紹（二）

目錄

背景

CLB布局（CLB Arrangement）

ASMBL Architecture

CLB Slices

CLB/Slice Configurations

Slice Description

Look-Up Table (LUT)

Storage Elements

Control Signals

背景

本博文是上篇博文的續(xù)集：Xilinx? 7 series FPGAs CLBs專題介紹（一），由于博文太長(zhǎng)了閱讀起來(lái)不太方便，所以這篇博文單獨(dú)出來(lái)。

在數(shù)據(jù)手冊(cè)上看到這個(gè)簡(jiǎn)單地總結(jié)目錄還是不錯(cuò)的，這里貼出來(lái)并且按照這個(gè)目錄來(lái)進(jìn)行分別介紹：

This chapter provides a detailed view of the 7 series FPGAs CLB architecture. These details can be useful for design optimization and verification, but are not necessary for initiating a design. This chapter includes:

? CLB Arrangement

Overview of slice locations and features within the CLB

? Slice Description

Complete details of SLICEM and SLICEL

? Look-Up Table (LUT)

Description of the logical function generators

? Storage Elements

Description and controls for the latches and flip-flops

? Distributed RAM (Available in SLICEM Only)

SLICEM ability to use LUTs as writable memory

? Shift Registers (Available in SLICEM Only)

SLICEM ability to use LUTs as shift registers

? Multiplexers

Dedicated gates for combining LUTs into wide functions

? Carry Logic

Dedicated gates and cascading to implement efficient arithmetic functions.

本章提供了7系列FPGA CLB架構(gòu)的詳細(xì)視圖。 這些細(xì)節(jié)可用于設(shè)計(jì)優(yōu)化和驗(yàn)證，但不是啟動(dòng)設(shè)計(jì)所必需的。

CLB布局（CLB Arrangement）

主要講述CLB中的Slice的位置以及特征的概述；

The CLBs are arranged in columns in the 7 series FPGAs. The 7 series is the fourth generation to be based on the unique columnar approach provided by the ASMBL? architecture.

CLB在7系列FPGA中按列排列。 7系列是第四代基于ASMBL?架構(gòu)提供的獨(dú)特柱狀方法。

ASMBL Architecture

Xilinx created the Advanced Silicon Modular Block (ASMBL) architecture to enable FPGA platforms with varying feature mixes optimized for different application domains. Through this innovation Xilinx offers a greater selection of devices, enabling customers to select the FPGA with the right mix of features and capabilities for their specific design.

Figure 2-1 provides a high-level description of the different types of column-based resources.

Xilinx創(chuàng)建了高級(jí)硅模塊（ASMBL）架構(gòu)，使FPGA平臺(tái)具有針對(duì)不同應(yīng)用領(lǐng)域優(yōu)化的各種功能組合。 通過(guò)這項(xiàng)創(chuàng)新，賽靈思提供了更多的器件選擇，使客戶能夠根據(jù)特定設(shè)計(jì)選擇具有適當(dāng)特性和功能的FPGA。圖2-1提供了不同類型的基于列的資源的高級(jí)描述。

從上圖可以看出，通過(guò)高級(jí)硅模塊（ASMBL）架構(gòu)（Architecture），在不同的領(lǐng)域（上圖為領(lǐng)域A、B、C）集成了不同的功能塊，使之適合于不同領(lǐng)域的不同需求，例如根據(jù)這些差別，Xilinx將7系列的FPGA分為了4種小的系列，每個(gè)系列又有很多中不同的型號(hào)的FPGA。

Xilinx? 7 series FPGAs comprise four FPGA families:

Spartan?-7 Family

Artix?-7 Family

Kintex?-7 Family

Virtex?-7 Family

例如virtex_7中有xc7vx690t等，更多分法見(jiàn)：Xilinx? 7 series FPGAs Overview，或官方數(shù)據(jù)手冊(cè)：http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf。

CLB Slices

A CLB element contains a pair of slices, and each slice is composed of four 6-input LUTs and eight storage elements.

? SLICE(0) – slice at the bottom of the CLB and in the left column

? SLICE(1) – slice at the top of the CLB and in the right column

These two slices do not have direct connections to each other, and each slice is organized as a column. Each slice in a column has an independent carry chain.

一個(gè)CLB包含一對(duì)slice，并且每個(gè)slice由4個(gè)6輸入的LUT和8個(gè)存儲(chǔ)器件。

SLICE（0）：位于CLB的底部且在左邊一列，又稱為SLICEL；

SLICE（1）：位于CLB的頂部且在右邊一列，又稱為SLICEM；

這兩個(gè)SLICE相互之間沒(méi)有直接的連接，并且每一個(gè)SLICE都被組織為一列。每個(gè)SLICE都有一個(gè)獨(dú)立的進(jìn)位鏈。

如下圖示：

上圖中的X0Y1、X0Y0等都是什么意思呢？

簡(jiǎn)單地說(shuō)X以及后面的一個(gè)數(shù)字代表的是一個(gè)slice的列的位置，從左往右開(kāi)始計(jì)數(shù)（0,1,2,3，...）；

Y以及后面的數(shù)字代表的是一個(gè)slice的行的位置，從下往上依次計(jì)數(shù)（0,1...）;

下面是數(shù)據(jù)手冊(cè)原話：

The Xilinx tools designate slices with these definitions:

? An “X” followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc.

? A “Y” followed by a number identifies a row of slices. The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom.

Xilinx工具使用以下定義指定切片：

?后跟數(shù)字的“X”標(biāo)識(shí)一對(duì)中每個(gè)slice的位置以及slice的列位置。 “X”數(shù)從序列0,1（第一個(gè)CLB列）的底部開(kāi)始計(jì)數(shù)切片; 2,3（第二個(gè)CLB欄）; 等等

?后跟數(shù)字的“Y”表示一行切片。 CLB中的數(shù)字保持不變，但從底部開(kāi)始，從一個(gè)CLB行到下一個(gè)CLB行依次計(jì)數(shù)。

CLB/Slice Configurations

Table 2-1 summarizes the logic resources in one CLB. Each SLICEM LUT can be configured as a look-up table, distributed RAM, or a shift register.

表2-1總結(jié)了一個(gè)CLB中的邏輯資源。 每個(gè)SLICEM LUT都可以配置為查找表，分布式RAM或移位寄存器。

表的下面還貼心的重復(fù)了這個(gè)問(wèn)題：僅限SLICEM，SLICEL沒(méi)有分布式RAM或移位寄存器。

Slice Description

Every slice contains:

? Four logic-function generators (or look-up tables)

? Eight storage elements

? Wide-function multiplexers

? Carry logic

These elements are used by all slices to provide logic, arithmetic, and ROM functions. In addition, some slices support two additional functions: storing data using distributed RAM and shifting data with 32-bit registers. Slices that support these additional functions are called SLICEM; others are called SLICEL.

每個(gè)切片包含：

?四個(gè)邏輯函數(shù)發(fā)生器（或查找表）

?八個(gè)存儲(chǔ)元件

?寬功能多路復(fù)用器

?進(jìn)位邏輯

所有slice都使用這些元素來(lái)提供邏輯，算術(shù)和ROM功能。 此外，一些slice支持兩個(gè)附加功能：使用分布式RAM存儲(chǔ)數(shù)據(jù)和使用32位寄存器移位數(shù)據(jù)。 支持這些附加功能的slice稱為SLICEM; 其他人被稱為SLICEL。

Look-Up Table (LUT)

The function generators in 7 series FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement:

? Any arbitrarily defined six-input Boolean function

? Two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs

? Two arbitrarily defined Boolean functions of 3 and 2 inputs or less

A six-input function uses:

? A1-A6 inputs

? O6 output

Two five-input or less functions use:

? A1–A5 inputs

? A6 driven High

? O5 and O6 outputs

7系列FPGA中的函數(shù)發(fā)生器實(shí)現(xiàn)為六輸入查找表（LUT）。 對(duì)于slice（A，B，C和D）中的四個(gè)函數(shù)發(fā)生器中的每一個(gè)，存在六個(gè)獨(dú)立輸入（A輸入-A1至A6）和兩個(gè)獨(dú)立輸出（O5和O6）。 函數(shù)發(fā)生器可以實(shí)現(xiàn)：

?任意定義的六輸入布爾函數(shù)

?兩個(gè)任意定義的五輸入布爾函數(shù)，只要這兩個(gè)函數(shù)共享公共輸入

?兩個(gè)任意定義的3和2輸入或更少的布爾函數(shù)

六輸入功能使用：

?A1-A6輸入

?O6輸出

兩個(gè)五輸入或更少的功能使用：

?A1-A5輸入

?A6驅(qū)動(dòng)高

?O5和O6輸出

The propagation delay through a LUT is independent of the function implemented. Signals from the function generators can:

? Exit the slice (through A, B, C, D output for O6 or AMUX, BMUX, CMUX, DMUX output for O5)

? Enter the XOR dedicated gate from an O6 output

? Enter the carry-logic chain from an O5 output

? Enter the select line of the carry-logic multiplexer from O6 output

? Feed the D input of the storage element

? Go to F7AMUX/F7BMUX wide multiplexers from O6 output

In addition to the basic LUTs, slices contain three multiplexers (F7AMUX, F7BMUX, and F8MUX). These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice.

? F7AMUX: Used to generate seven input functions from LUTs A and B

? F7BMUX: Used to generate seven input functions from LUTs C and D

? F8MUX: Used to combine all LUTs to generate eight input functions.

Functions with more than eight inputs can be implemented using multiple slices. There are no direct connections between slices to form function generators greater than eight inputs within a CLB.

通過(guò)LUT的傳播延遲與實(shí)現(xiàn)的功能無(wú)關(guān)。

來(lái)自函數(shù)發(fā)生器的信號(hào)可以：

?退出切片（通過(guò)A，B，C，D輸出為O6或AMUX，BMUX，CMUX，DMUX輸出為O5）

?從O6輸出進(jìn)入XOR專用門

?從O5輸出進(jìn)入進(jìn)位邏輯鏈

?從O6輸出進(jìn)入進(jìn)位邏輯多路復(fù)用器的選擇線

?輸入存儲(chǔ)元件的D輸入

?從O6輸出轉(zhuǎn)到F7AMUX / F7BMUX寬多路復(fù)用器

除基本LUT外，Slice還包含三個(gè)多路復(fù)用器（F7AMUX，F(xiàn)7BMUX和F8MUX）。這些多路復(fù)用器用于組合多達(dá)四個(gè)函數(shù)發(fā)生器，以提供片中七個(gè)或八個(gè)輸入的任何功能。

?F7AMUX：用于從LUT A和B生成七個(gè)輸入功能

?F7BMUX：用于從LUT C和D生成七個(gè)輸入功能

?F8MUX：用于組合所有LUT以生成八個(gè)輸入功能。

可以使用多個(gè)切片實(shí)現(xiàn)具有八個(gè)以上輸入的功能。切片之間沒(méi)有直接連接，以在CLB內(nèi)形成大于8個(gè)輸入的函數(shù)發(fā)生器。

Storage Elements

There are eight storage elements per slice. Four can be configured as either edge-triggered D-type flip-flops or level-sensitive latches.

The D input can be driven directly by a LUT output via AFFMUX, BFFMUX, CFFMUX, or DFFMUX, or by the BYPASS slice inputs bypassing the function generators via AX, BX, CX, or DX input. When configured as a latch, the latch is transparent when the CLK is Low.

每個(gè)slice有8個(gè)存儲(chǔ)元件。其中4個(gè)可以被配置成沿觸發(fā)的D觸發(fā)器或電平觸發(fā)的鎖存器。

D輸入可由LUT輸出通過(guò)AFFMUX，BFFMUX，CFFMUX或DFFMUX直接驅(qū)動(dòng)，或通過(guò)BYPASS slice（？？？這是啥？）輸入繞過(guò)函數(shù)發(fā)生器（LUT）通過(guò)AX，BX，CX或DX輸入。 當(dāng)配置為鎖存器時(shí)，當(dāng)CLK為低電平時(shí)，鎖存器是透明的。

There are four additional storage elements that can only be configured as edge-triggered D-type flip-flops.

The D input can be driven by the O5 output of the LUT or the BYPASS slice inputs via AX, BX, CX, or DX input. When the original four storage elements are configured as latches, these four additional storage elements cannot be used.

另外4個(gè)存儲(chǔ)元件只能被配置成沿觸發(fā)的D觸發(fā)器。D輸入可以由LUT的輸出O5驅(qū)動(dòng)，或者BYPASS slice輸入通過(guò)AX，BX，CX或DX輸入。當(dāng)原來(lái)的4個(gè)存儲(chǔ)元件被配置成鎖存器時(shí)，另外4個(gè)額外的存儲(chǔ)元件就不能被使用。

上面的關(guān)于D輸入的驅(qū)動(dòng)問(wèn)題可能有些難理解，給出這張圖幫助一下理解，第一個(gè)圖是只能配置成觸發(fā)器的圖，第二個(gè)是：既可以配置成觸發(fā)器又可以配置成鎖存器的圖。

Control Signals

The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice. When one flip-flop in a slice has SR or CE enabled, the other flip-flops used in the slice also have SR or CE enabled by the common signal. Only the CLK signal has programmable polarity. Any inverter placed on the clock signal is automatically absorbed. The CE and SR signals are active-High.

控制信號(hào)時(shí)鐘（CLK），時(shí)鐘使能（CE）和置位/復(fù)位（SR）對(duì)于一個(gè)片中的所有存儲(chǔ)元件是公共的。 當(dāng)切片中的一個(gè)觸發(fā)器啟用SR或CE時(shí)，切片中使用的其他觸發(fā)器也具有由公共信號(hào)啟用的SR或CE。 只有CLK信號(hào)具有可編程極性。 放置在時(shí)鐘信號(hào)上的任何反相器都會(huì)被自動(dòng)吸收。 CE和SR信號(hào)為高電平有效。

These initialization options are available for storage elements:

? SRLOW: Synchronous or asynchronous Reset when CLB SR signal is asserted

? SRHIGH: Synchronous or asynchronous Set when CLB SR signal is asserted

? INIT0: Asynchronous Reset on power-up or global Set/Reset

? INIT1: Asynchronous Set on power-up or global Set/Reset

The SR signal forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic High at the storage element output when SR is asserted, while SRLOW forces a logic Low at the storage element output

這些初始化選項(xiàng)對(duì)存儲(chǔ)元件有效：

? SRLOW: 當(dāng)CLB SR信號(hào)有效時(shí)，同步或異步復(fù)位；

? SRHIGH: 當(dāng)CLB SR信號(hào)有效時(shí)，同步或異步置位。

?INIT0：上電或全局置1 /復(fù)位時(shí)的異步復(fù)位

?INIT1：上電或全局置1 /復(fù)位時(shí)異步置位

SR信號(hào)強(qiáng)制存儲(chǔ)元件進(jìn)入SRHIGH或SRLOW屬性指定的狀態(tài)。 當(dāng)SR被置位時(shí)，SRHIGH強(qiáng)制存儲(chǔ)元件輸出處的邏輯高電平，而SRLOW強(qiáng)制存儲(chǔ)元件輸出處的邏輯低電平

下表為真值表：

看來(lái)這篇博文也寫(xiě)不完了，剩下的內(nèi)容等到下一篇博文吧。

FPGA

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